High resolution time stamps are one thing, accurate world time is a completely different topic. Our systems have 3.2nsec resolution hardware timestamp, however this is the timer resolution not the accuracy of keeping world time. For precise global time we support stock PTPv2 and PTPv2 augmented with a PPS (pulse-per-second) signal. As we will see below PTPv2 gives ~100nsec synchronization levels and the accuracy of PTPv2+PPS will is discussed separately.

After months of slaving away, problem after problem finally, yes finally! fmadio40 the 1x40G or 4x10G line rate packet capture system gets its first demo in RL (real life). There`s a lot of info on the blog about the system but its completely different when your there talking with a real live person about what’s great, what’s ok and what sucks.

We`ve spent a fair amount of time talking about our capture hardware so lets switch gears and dig into the software interface. Interaction with our 10G, 40G and 100G ethernet capture systems is over HTTP or HTTPS. You can use a web browser on port 80 or CURL and HTTPS on port 1337, its completely configurable and only uses a single TCP port. Alternatively there is also a WebDAV interface if your deep in the colo and without a browser.

SSD`s are the life blood of our fmadio 10G, 40G, 100G ethernet capture systems. They provide backing storage that well exceeds that of conventional RAM, are super fast and light weight. Thus its prudent to keep the SSD farms in top nick, optimal health, and occasionally perform emergency room brain surgery on them. Unfortunately today is one of those days.

Finally after weeks of searching, designing and plenty of cursing, Chassis Number One has finally arrived at the office! Its been surprisingly frustrating as the market for low volume customized chassis is hmmm... small. Luckily we did find a company in the US of A (of all places) which specializes in exactly that, low volume high quality custom chassis.

Bit encoding is an art unto itself, where there`s plenty of different encoding schemes to choose from. There`s 8b/10b encoding of PCIexpress Version 2, the 128b/130b encoding of PCIExpress Version 3, 64b/67b of interlaken and of course stock 64b/66b encoding used in all 10G, 40G and 100G ethernet protocols.

The XGMII protocol is a formalized way for two hardware blocks (typically the MAC & PHY) to communicate when a packet starts/ends and if there`s any errors detected on the line. The full spec is defined in IEEE 802.3 Clause 46 but we will save you the legalize parse time and explain it in plain English.

Think your`re an networking ethernet guru ? tcpdump kung fu master? eat jumbo packets for breakfast? Then welcome to the "Layer 1" dungeon, forget everything you know. We are talking about transceiver, clock recovery, DC balance, encoding symbol sets, scrambling, lane skew and more. For 10G, 40G and 100G networks you will be surprised that, what data you think is going down the wire, is actually a completely different set of 1`s and 0`s in the cable.

あなたはネットワーキングイーサネットの天才？tcpdumpカンフーマスター？それとも朝ごはんにジャンボパケットを食べますか？それであれば「レイヤ1」迷宮へようこそ。あなたの知識を全て忘れてください。私たちは、トランシーバ、クロック・リカバリ、DCバランス、エンコーディングシンボルセット、スクランブル、レーンスキューなどについて話します。10G、40G、100Gネットワークでは、あなたが配線を通ると思っているデータが実際はケーブルないでは完全に異なる1や0であることに驚くでしょう。

Ladies and gentlemen... Start your engines!